Memristive Devices for Time Domain Compute-in-Memory
Time is continuous and adds up. The team Florian Freye, Jie Lou and Prof. Tobias Gemmeke from the IDS of RWTH Aachen University uses this simple insight for the development of neuromorphic circuits within the NEUROTEC project. These are fundamentally built on the concept of computing in memory (CIM) - a paradigm from neuromorphic computing that is oriented towards the human brain and overcomes the conventional von Neumann computer architecture with separation of memory and processor. The added trick here: It is not charges or currents that are added, but time delays. Together, this results in the novel concept of Time-Domain Computing-in-Memory (TD-CIM).
A major innovation now is the realization of the delays with programmable resistors as researched by the team of Christopher Bengel (IWE2, RWTH) as well as Stephan Menzel, and Stefan Wiefels (PGI-7, FZJ) at FZJ.
To do this, a discrete signal is delayed as it passes through a network of digital delay elements corresponding to the programmable resistor value. The resulting signal has accumulated the time delay of the sum of the individual delays. Because of the advantageous properties of a small area requirement and the leakage-free (non-volatile) storage of the resistance value, so-called memristive elements are used as memory by the FZJ.
The Jülich researchers have great expertise in characterizing and modeling such memristive elements, which are based on the valence change mechanism (VCM) and form tiny filamentary conducting compounds in the insulating metal oxide between two metal electrodes. These memristive elements can be programmed in resistance value. When fabricated, they are integrated as top-level structures on a CMOS circuit, which eliminates the area requirements of the memory. A challenging property of these elements is their relatively large variability from element to element, as well as in the setting operations within an element. Switching failures also occur.
As part of the joint research, the calibrated physical models of the novel VCM devices - including the effects of variability and reliability - were integrated into the behavioral model of the TD-CIM circuit. A detailed analysis showed the performance in your use in bitwise and multi-bit realizations in terms of neural network classification accuracy. The promising results: At comparable power consumption, the area was significantly reduced compared to pure CMOS/implementations. Although the signal-to-noise ratio at nominal voltage is currently still too high, it scales significantly better than classical CMOS/solutions at reduced supply voltage. While the binary case is already competitive, the use for multibit requires further improvement of the memristive switching devices.
