WP5 Concepts for Neuromorphic Circuits
The goal of work package 5 is to build neuromorphic circuits. You can think of it being a bridge between all the materials and devices work in AP1-4 and the application work especially in work package 6. It is a big extension to the AP5 in NEUROTEC-I. We have moved up to seven work packages and all of these will feed into the chip demonstrators (in DP). There are three general level approaches that are being explored: Beyond Moore, More Moore and Design-Technology Co-optimization :
1) AP5.1-AP5.5, the Beyond Moore approach: The Idea is to take CMOS with memristive hardware and built new hybrid analog/digital circuits.
2) AP5.6 follows the More Moore approach: The idea is to build neuromorphic circuits with digital CMOS.
3) AP5.7 follows a high level DTCO (Design-Technology Co-optimization) approach combining hybrid memristive hardware with digital components.
In this work package the "classic" DTCO will be expanded to the new features of memristive devices.
While classic DTCO seeks technological optimization, in order to improve the KPI of the Fixed Logic Design and focuses on the interplay between ISA ⇄ Software, neuromorphic DTCO solves problems of use cases and focuses on the quality of result metrics. It applies optimization on all levels of design hierarchy including the material substrates in the device level. For this quantitative models are needed to exchange the necessary information between design levels.
The evaluation of functionality of memristive elements will be done by measuring the performance of selected functional blocks:
AP5.1: Memrisitve Accellerators for analog Computation-In-Memory
AP5.2: Memristor based analog TCAM-blocks
AP5.3: Memristor based functional Spiking Neural Network -building blocks
AP5.4: Probabilistic Computing
AP5.5: Analysis of neuromorphic Hardware Security
As examples the following 4 Areas are addressed: Fundamental data base functionality (min, max, sort, CAM, dynamic programming), linear algebra, pulsed neuronal networks and basic functions of security mechanisms.
AP5.6 (: SoC Entwurf More Moore) offers a programmable platform with key functionality: RISC-V-based, 22-nm-FDX-technology and additional neuromorphic accelerators as a CMOS-baseline.
A validation will be done in Demonstrators (D1, D2, SoC und SoC+), where the physical boards are realized separately for „More Moore“- and „Beyond Moore“-technology.