The need
In conventional von Neumann computing architectures, communication between the CPU and memory decreases the system's overall performance. Compute-in-memory (CIM), one of the neuromorphic paradigms, overcomes this memory wall, thus increasing the speed and energy efficiency of computing.
Key Features
- Compute In Memory (CIM) arrays with non-volatile memory devices based on memristors arranged in crossbar matrices
- 1T1R (one transistor and one memristor in series) T is for selection and current compliance
- NMOS transistors 5V size W/L = 20 (W = 10 µm, L = 500 nm), as well as W/L = 1 (W = 10 µm, L = 10 µm)
- VCM type memristors:
100 nm x 100 nm-sized Pt/3 nm HfO2/3 nm TiOx/10 nm Ti/Pt devices produced in >30 processing steps
Impact
- Towards manufacturability: Successfull testing of the back-end-of-line fabrication process of the memristive devices at metal layer 5 on 180nm node CMOS (FEOL: XFAB).
- Device Optimization: Characterization and physical modelling of transient memristive device behaviour leads to improved programming schemes reducing the variability of the set value.
Read more: https://doi.org/10.1002/aelm.202500891
This publication will be presented as an ICNCE-2026 poster
- Application: One use case of the chip is a compute-in-memory accelerator for a Kolmogorov–Arnold network. In terms of energy-delay product, it provides a 1996x improvement over CPUs, a 208x improvement over conventional multilayer perceptrons and a 71x improvement over prior KAN accelerators.
Read more: https://doi.org/10.1002/aisy.202501220 - Application: Logic-in-memory (LiM) has emerged as a promising paradigm to address the von Neumann bottleneck by integrating data storage and in-situ computation. We experimentally demonstrate a CMOS-integrated TaOx-based 1T1R RRAM computing fabric that supports reconfigurable LiM operations, including a functionally complete Boolean set and in-memory arithmetic primitives.
Read more: https://doi.org/10.1088/2634-4386/ae65d5
Demonstrator Chip NEUROTEC-I
Letzte Änderung: 25.06.2026
