Demonstrator Chip SoC

The need

In neuromorphic computing hardware there is an alternative approach to using memristors. This "More Moore" concept exploits the ongoing advancement of Moore's law for energy efficiency and overal device-technology optimization. The system on a chip (SoC) will be used to interface with Orca-D2 for benchmarks.

Key Features

  • MoreMoore SoC was manufactured in 22nm FDSOI technology by Global Foundries
  • MoreMoore SoC includes multiple accelerators, a processor, shared SRAM memory and a chip-to-chip communication interface
  • MoreMoore SoC was measured and validated which resulted in multiple publications [1],[2],[3],[4]
  • Measurement results are used to optimize cost-benefit function
Die-shot with highlighted test array.

Impact

  • Publications:
  • [1] J. Lou, F. Freye, C. Lanius and T. Gemmeke, "An All-Digital Time-Domain Compute-in-Memory Engine for Convolutional Neural Networks in 22nm," 2025 IEEE International Symposium on Circuits and Systems (ISCAS), London, United Kingdom, 2025, pp. 1-5, doi: 10.1109/ISCAS56072.2025.11043778.

    [2] Lou, Jie, et al. "A 22nm 96.83-TOPS/W Time-Domain Compute-in-Memory Engine Utilizing Mixed-Fidelity for Edge-AI Applications." Proceedings of the Great Lakes Symposium on VLSI 2025. 2025.

    [3] F. Freye, C. Lanius, N. Mutert and T. Gemmeke, "4T Bitcell for Digital Compute-in-Memory," 2025 IEEE Nordic Circuits and Systems Conference (NorCAS), Riga, Latvia, 2025, pp. 1-7, doi: 10.1109/NorCAS66540.2025.11231198.

    [4] Lanius, Christian, Florian Freye, and Tobias Gemmeke. "A 1.27 fJ/B/transition Digital Compute-in-Memory Architecture for Non-Deterministic Finite Automata Evaluation." Proceedings of the Great Lakes Symposium on VLSI 2025. 2025.

Demonstrator Chip SoC

Letzte Änderung: 25.06.2026