For Compute-in-Memory (CIM) approaches the matrix weight factors are stored in resistive memory crossbar arrays. The size of individual arrays is limited by leak current effects scaling with array size. In order to realize different network types with variable number of layers and layer sizes the crossbar circuits need to be combined in an adjustable way, for example to be connected in series or in parallel. As a consequence, the chip has to be designed in a flexible and programmable way.

• The ORCA-D1 Chip is the most complex tape-out (June 2026) ever done at the Forschungszentrum Jülich:
  >65000 memristors, and >2500 ADCs on one single CMOS chip
  
• The ORCA-D1 Chip and its successor ORCA-D2 will be used as an R&D platform for a variety of feasibility tests and benchmarking for hardware-algorithm co-designed neuromorphic approaches to learning (rules), optimization algorithms, transformers, artificial intelligence etc. ORCA-D1 focusses on Compute In Memory (CIM) and still needs an external RISC-V processor for programming.
  
• Learn more about the ORCA concept development via virtual platforms at ICNCE 2026 Poster Session.
  Poster Abstract (PDF): Virtual Platforms for the ORCA Chip Architecture: Two Perspectives